1. Field of the Invention
The present invention generally relates to A/D converters and systems having A/D (analog-to-digital) converters, and particularly relates to a parallel-type A/D converter and a system having such a parallel-type A/D converter.
2. Description of the Related Art
A parallel-type A/D converter of an 8-bit configuration, for example, includes 255 converters, each of which receives respective reference potentials obtained by a resister-based potential divider. These 255 converters compare the respective reference potentials with an input potential, thereby converting the input potential into a digital value.
FIG. 1 is a circuit diagram showing a configuration of a comparator used in a parallel-type A/D converter.
The comparator of FIG. 1 includes a PMOS transistor 11, an NMOS transistor 12, a buffer 13, an inverter 14, switches S1 through S3, and a condenser C1. The buffer 13 and the inverter 14 generate control signals Φ1 and Φ2, respectively, from a clock signal CLK. By ignoring a slight delay, the control signal Φ1 can be regarded as having the same phase as the clock signal CLK, and the control signal Φ2 can be regarded as having the opposite phase to the clock signal CLK. The control signal Φ1 is supplied to the switches S1 and S3, and closes the switches S1 and S3 when the clock signal CLK is HIGH. The control signal Φ2 is supplied to the switch S2, and closes the switch S2 when the clock signal CLK is LOW.
When the switch S3 is closed to provide a path in response to the HIGH period of the clock signal CLK, the inverter comprised of the PMOS transistor 11 and the NMOS transistor 12 has the input thereof and the output thereof coupled together, so that a through electric current runs through the PMOS transistor 11 and the NMOS transistor 12 from a power supply potential VDD to the ground potential. When this happens, a potential at the input and output nodes of the inverter is set to VDD/2. The switch S1 is also closed at this time, thereby allowing an input potential VIN to charge the condenser C1.
When the switches S1 and S3 are open to sever the paths in response to the LOW period of the clock signal CLK, the switch S2 is closed to provide a path. The end of the condenser C1 that is connected to the switch S2 is set to a reference potential generated by a resistor series including resistors R1 and R2. This reference potential is lowered by the potential corresponding to the amount of electric charge accumulated in the condenser C1 (i.e., corresponding to the input potential VIN), followed by being supplied to the gates of the PMOS transistor 11 and the NMOS transistor 12.
If the input potential VIN is lower than the reference voltage, an output potential VOUT is set to LOW. If the input potential VIN is higher than the reference voltage, the output potential VOUT is set to HIGH. A plurality of output potentials VOUT output from the respective comparators arranged in parallel are then encoded and sampled, thereby performing A/D conversion.
As systems are implemented as LSI, nowadays, parallel-type A/D converters are beginning to be used in various frequencies. In order to satisfy such needs, a single A/D converter needs to cover a wide range of frequencies from a lower frequency to a higher frequency. To this end, provision has to be made to elongate the gate widths of the PMOS transistor 11 and the NMOS transistor 12, thereby allowing an electric current to freely flow even at high frequency.
If a configuration is made such as to be operable at high frequency, it will give rise to a problem in that the through electric current described above increases, resulting in large power consumption. An increase in power consumption at high frequency may have to be accepted as an unavoidable cost. At low frequency, however, there is no need to have a large current running through the circuit, and it is desirable to have as low power consumption as possible.
Power consumption by the through current running through the PMOS transistor 11 and the NMOS transistor 12 is constant in the parallel-type A/D comparator regardless of whether the operation frequency is high or low. Namely, the through current is present to incur power consumption during the HIGH period of the clock signal CLK, i.e., during half the total operation time, regardless of HIGH or LOW of the operation frequency.
In this manner, a configuration that is operable at higher frequency comes with a cost that power consumption increases also at lower frequency.
Accordingly, there is a need for an A/D comparator which is operable at higher frequency and operates with reduced power consumption at lower frequency, and there is also a need for a system including such an A/D comparator.